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1 p/n:pm1118 rev. 1.0, nov. 08, 2004 mx26lv040 4m-bit [512k x 8] cmos single voltage 3v only high speed eliteflash tm memory - automatically program and verify data at specified address ? status reply - data# polling & toggle bit for detection of program and erase operation completion. 2,000 minimum erase/program cycles latch-up protected to 100ma from -1v to vcc+1v package type: - 32-pin plcc - 32-pin tsop - 32-pin pdip compatibility with jedec standard - pinout and software compatible with single-power supply flash 20 years data retention features extended single - supply voltage range 3.0v to 3.6v 524,288 x 8 single power supply operation - 3.0v only operation for read, erase and program operation fast access time: 55/70ns low power consumption - 30ma maximum active current - 30ua typical standby current command register architecture - byte programming (55us typical) - sector erase (sector structure 64k-byte x8) auto erase (chip & sector) and auto program - automatically erase any combination of sectors with erase suspend capability. general description the mx26lv040 is a 4-mega bit flash memory orga- nized as 512k bytes of 8 bits. mxic's flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. the mx26lv040 is pack- aged in 32-pin plcc, 32-pin tsop and 32-pin pdip. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard mx26lv040 offers access time as fast as 55ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx26lv040 has separate chip enable (ce#) and output enable (oe#) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx26lv040 uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom compatibility. mxic flash technology reliably stores memory contents even after 2,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy- cling. the mx26lv040 uses a 3.0v~3.6v vcc supply to perform the high reliability erase and auto program/ erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up pro- tection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. macronix nbit tm memory family
2 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 pin configurations table 1. pin description symbol pin name a0~a18 address input q0~q7 data input/output ce# chip enable input we# write enable input oe# output enable input vcc power supply pin (3.0v~3.6v) gnd ground pin 32 plcc block structure table 2. mx26lv040 sector architecture sector sector size address range sector address byte mode byte mode (x8) a18 a17 a16 a15 a14 a13 sa0 64kbytes 00000-0ffff 0 0 0 x x x sa1 64kbytes 10000-1ffff 0 0 1 x x x sa2 64kbytes 20000-2ffff 0 1 0 x x x sa3 64kbytes 30000-3ffff 0 1 1 x x x sa4 64kbytes 40000-4ffff 1 0 0 x x x sa5 64kbytes 50000-5ffff 1 0 1 x x x sa6 64kbytes 60000-6ffff 1 1 0 x x x sa7 32kbytes 70000-7ffff 1 1 1 x x x 32 tsop 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe# a10 ce# q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 a18 vcc we# a17 mx26lv040 a11 a9 a8 a13 a14 a17 we# vcc a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx26lv040 32 pdip mx26lv040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we# a17 a14 a13 a8 a9 a11 oe# a10 ce# q7 q6 q5 q4 q3
3 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a18 ce# oe# we#
4 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 automatic programming the mx26lv040 is byte programmable using the auto- matic programming algorithm. the automatic program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and a0h) and a program command (program data and address). the device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. a status bit similar to data# polling and a status bit toggling between consecutive read cycles, provide feed- back to the user as to the status of the programming operation. refer to write operation status, table 7, for more information on these status bits. automatic chip erase the entire chip is bulk erased using 10 ms erase pulses according to mxic's automatic chip erase algorithm. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internally within the device. automatic sector erase the mx26lv040 is sector(s) erasable using mxic's auto sector erase algorithm. the automatic sector erase algorithm automatically programs the specified sector(s) prior to electrical erase. the timing and verification of electrical erase are controlled internally within the de- vice. an erase operation can erase one sector, multiple sectors, or the entire device. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecutive read cycles provides feedback to the user as to the sta- tus of the erasing operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we# or ce#, whichever happens first. mxic's flash technology combines years of eprom experience to produce the highest levels of quality, reli- ability, and cost effectiveness. the mx26lv040 electri- cally erases all bits simultaneously using fowler- nordheim tunneling. the bytes are programmed by us- ing the eprom programming mechanism of hot elec- tron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set. automatic select the auto select mode provides manufacturer and de- vice identification, through identifier codes output on q7~q0. this mode is mainly adapted for programming equipment on the device to be programmed with its pro- gramming algorithm. when programming by high voltage method, automatic select mode requires vid (11v to 12v) on address pin a9 and other address pin a6, a1 and a0 as referring to table 3. in addition, to access the auto- matic select codes in-system, the host can issue the automatic select command through the command regis- ter without requiring vid, as shown in table 4.
5 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 table 3. mx26lv040 auto select mode operation note:sa=sector address, x=don't care, l=logic low, h=logic high a18 a12 a9 a8 a6 a5 a1 a0 description ce# oe# we# | | | | q7~q0 a13 a10 a7 a2 read manuf acturer code l l h x x vid x l x l l c2h silicon id device id l l h x x vid x l x l h 4fh first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset 1 xxxh f0h read 1 ra rd read silicon id 4 555h aah 2aah 55h 555h 90h adi ddi program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h table 4. mx26lv040 command definitions note: 1. adi = address of device identifier; a1=0, a0 = 0 for manufacturer code,a1=0, a0 = 1 for device code. a2-a18=do not care. (refer to table 3) ddi = data of device identifier : c2h for manufacture code, 4fh for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address of the sector. 3. address a18-a11 are don't cares for unlock and command cycles. command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 4 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress.
6 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 table 5. mx26lv040 bus operation notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 4. 2. vid is the silicon-id-read high voltage, 11v to 12v. 3. refer to table 4 for valid data-in during a write operation. 4. x can be vil or vih. address description ce# oe# we# a18 a12 a9 a8 a6 a5 a1 a0 q0~q7 a13 a10 a7 a2 write l h l ain din(3) reset x x x x high z output disable l h h x high z standby vcc 0.3v x x x high z
7 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to vil. ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at vih. the internal state machine is set for reading array data upon device power-up. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. write commands/command sequences to program data to the device or erase sectors of memory , the system must drive we# and ce# to vil, and oe# to vih. the "byte program command sequence" section has details on programming data to the device. an erase operation can erase one sector, multiple sectors , or the entire device. table indicates the address space that each sector occupies. a "sector address" consists of the address bits required to uniquely select a sector. the "writing specific address and data commands or sequences into the command register initiates device operations. table 1 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on q7-q0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence section for more information. icc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification table and timing diagrams for write operations. standby mode when using both pins of ce#, the device enter cmos standby with both pins held at vcc 0.3v. if ce# is held at vih, but not within the range of vcc 0.3v, the device will still be in the standby mode, but the standby current will be larger. during auto algorithm operation, vcc active current (icc2) is required even ce# = "h" until the operation is completed. the device can be read with standard access time (tce) from either of these standby modes, before it is ready to read data. output disable with the oe# input at a logic high level (vih), output from the devices are disabled. this will cause the output pins to be in a high impedance state. read command the read operation is initiated by writing the read com- mand sequence into the command register. microproc- essor read cycles retrieve array data. the device re- mains enabled for reads until the command register con- tents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid com- mand must then be written to place the device in the desired state. silicon-id read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage (vid). however, multiplexing high voltage onto address lines is not generally desired system de- sign practice. the mx26lv040 contains a silicon-id-read operation to supple traditional prom programming methodology. the operation is initiated by writing the read silicon id com-
8 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 mand sequence into the command register. set-up automatic chip/sector erase commands chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h or sector erase command 30h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the auto- matic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pat- tern, a self-timed chip erase and verify begin. the erase and verify operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). if the erase operation was unsuccessful, the data on q5 is "1"(see table 7), indicating the erase operation ex- ceed internal timing limit. the automatic erase begins on the rising edge of the last we# or ce# pulse, whichever happens first in the com- mand sequence and terminates when the data on q7 is "1" and the data on q6 stops toggling for two consecu- tive read cycles, at which time the device returns to the read mode.
9 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 reading array data the device is automatically set to reading array data after device power-up. no commands are required to re- trieve data. the device is also ready to read array data after completing an automatic program or automatic erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. af- ter completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more information on this mode. the system must issue the reset command to re-en- able the device for reading array data if q5 goes high, or while in the autoselect mode. see the "reset command" section, next. reset command writing the reset command to the device resets the device to reading array data. address bits are don't care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be-fore programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an silicon id read command pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code(hex) manufacture code vil vil 1 1 0 00010c2h device code vih vil 0 1 0 011114fh table 6. silicon id code sequence. once in the silicon id read mode, the reset command must be written to return to reading array data (also applies to silicon id read during erase suspend). if q5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). sector erase commands the automatic sector erase does not require the device to be entirely pre-programmed prior to executing the au- tomatic sector erase set-up command and automatic sector erase command. upon executing the automatic sector erase command, the device will automatically program and verify the sector(s) memory for an all-zero data pattern. the system is not required to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the de- vice returns to the read mode. the system is not re- quired to provide any control or timing during these op- erations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up com- mand 80h. two more "unlock" write cycles are then fol- lowed by the sector erase command 30h. the sector address is latched on the falling edge of we# or ce#, whichever happens later, while the command (data) is latched on the rising edge of we# or ce#, whichever happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we# or
10 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 ce#, whichever happens later. each successive sector load cycle started by the falling edge of we# or ce#, whichever happens later must begin within 50us from the rising edge of the preceding we# or ce#, whichever happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase(30h) or erase suspend(b0h) during the time-out period resets the device to read mode. byte program command sequence the device programs one byte of data for each program operation. the command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not re- quired to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 1 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using q7, q6. see "write operation status" for information on these status bits. any commands written to the device during the embed- ded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a "0" back to a "1". attempting to do so may halt the op- eration and set q5 to "1" or cause the data# polling algo- rithm to indicate the operation was successful. however, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1". write operation status the device provides several bits to determine the sta- tus of a write operation: q2, q3, q5, q6, q7. table 7 and the following subsections describe the functions of these bits. q7 and q6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. q7: data# polling the data# polling bit, q7, indicates to the host system whether an automatic algorithm is in progress or com- pleted, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the automatic program algorithm, the device out- puts on q7 the complement of the datum programmed to q7. this q7 status also applies to programming during erase suspend. when the automatic program algorithm is complete, the device outputs the datum programmed to q7. the system must provide the program address to read valid status information on q7. during the automatic erase algorithm, data# polling pro- duces a "0" on q7. when the automatic erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a "1" on q7. this is analo- gous to the complement/true datum out-put described for the automatic program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". the system must provide an address within any of the sectors se- lected for erasure to read valid status information on q7. when the system detects q7 has changed from the complement to true data, it can read valid data at q7-q0 on the following read cycles. this is because q7 may change asynchronously with q0-q6 while output enable (oe#) is asserted low. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete. toggle bit i may be read at any address, and is valid after the rising edge of the final we# or ce#, whichever happens first, in the command sequence (prior to the program or erase operation), and during the sector time-out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe# or ce# to
11 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 control the read cycles. when the operation is complete, q6 stops toggling. when the device is actively erasing (that is, the auto- matic erase algorithm is in progress), q6 toggling. how- ever, the system must also use q2 to determine which sectors are erasing. alternatively, the system can use q7. q6 stops toggling once the automatic program algorithm is complete. table 7 shows the outputs for toggle bit i on q6. q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase algorithm is in process), or whether that sector is erase-suspended. toggle bit ii is valid af- ter the rising edge of the final we# or ce#, whichever happens first, in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by com- parison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 7 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has com- pleted the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase opera- tion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the al- gorithm when it returns to determine the status of the operation. q5: exceeded timing limits q5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not suc- cessfully completed. data# polling and toggle bit are the only operating functions of the device under this con- dition. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector maynot be re- used, (other sectors are still functional and can be re- used). the time-out condition will not appear if a user tries to program a non blank location without erasing. please note that this is not a device failure condition since the device was incorrectly used.
12 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 status q7 q6 q5 q3 q2 (note1) (note2) in byte program in auto program algorithm q7# toggle 0 n/a no toggle progress auto erase algorithm 0 toggle 0 1 toggle exceeded byte program in auto program algorithm q7# toggle 1 n/a no toggle time limits auto erase algorithm 0 toggle 1 1 toggle table 7. write operation status note: 1. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. q5 switches to '1' when an auto program or auto erase operation has exceeded the maximum timing limits. see "q5 : exceeded timing limits" for more information.
13 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 pow er supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd. power-up sequence the mx26lv040 powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command se- quences. q3 sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data# polling and toggle bit are valid after the initial sector erase com- mand sequence. if data# polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data# polling or toggle bit. if q3 is low ("0"), the device will accept additional sector erase commands. to insure the com- mand has been accepted, the system software should check the status of q3 prior to and following each sub- sequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. data protection the mx26lv040 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe- cific command sequences. the device also incorporates several features to prevent inadvertent write cycles re- sulting from vcc power-up and power-down transition or system noise. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce# or we# will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe# = vil, ce# = vih or we# = vih. to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one.
14 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9 and oe# (note 2) . . . . . . . . . . . -0.5 v to +12 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. maxi- mum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may over- shoot to vcc +2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9 and oe# is -0.5v. during voltage transitions, a9 and oe# may overshoot vss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 is +12v which may overshoot to 13.5v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +3.0 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
15 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 capacitance ta = 25 o c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin1 input capacitance 8 pf vin = 0v cin2 control pin capacitance 12 pf vin = 0v cout output capacitance 12 pf vout = 0v notes: 1. vil min. = -1.0v for pulse width is equal to or less than 50 ns. vil min. = -2.0v for pulse width is equal to or less than 20 ns. 2. vih max. = vcc + 1.5v for pulse width is equal to or less than 20 ns if vih is over the specified maximum value, read operation cannot be guaranteed. 3. automatic sleep mode enable the low power mode when addresses remain stable for tacc +30ns. table 8. dc characteristics ta = 0 o c to 70 o c, vcc = 3.0v ~ 3.6v symbol p arameter min. typ max. unit conditions ili input leakage current 1 ua vin = vss to vcc ilit a9 input leakage current 100 ua vcc=vcc max; a9=12v ilo output leakage current 1 ua vout = vss to vcc, vcc = vcc max icc1 vcc active read current 20 30 ma ce#=vil, @5mhz 8 14 ma oe#=vih @1mhz icc2 vcc active write current 26 30 ma ce#=vil, oe#=vih icc3 vcc standby current 30 100 ua vil input low voltage (note 1) -0.5 0.8 v vih input high voltage 0.7xvcc vcc+ 0.3 v vid voltage for automative 11 12 v vcc=3.3v select vol output low voltage 0.45 v iol = 4.0ma, vcc = vcc min voh1 output high voltage(ttl) 0.85xvcc ioh = -2ma, vcc =vcc min voh2 output high voltage vcc-0.4 ioh = -100ua, vcc min (cmos)
16 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 26l v040-55 26l v040-70 symbol parameter min. max. min. max. unit conditions trc read cycle time (note 1) 55 70 ns tacc address to output delay 55 70 ns ce#=oe#=vil tce ce# to output delay 55 70 ns oe#=vil toe oe# to output delay 25 30 ns ce#=vil tdf oe# high to output float (note1) 0 25 0 30 ns ce#=vil toeh output enable read 0 0 ns hold time toggle and data# polling 10 10 ns toh address to output hold 0 0 ns ce#=oe#=vil note: 1. not 100% tested. 2. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: input pulse levels: 0v/3.0v. input rise and fall times is equal to or less than 5ns. output load: 1 ttl gate + 100pf (including scope and jig), for 26lv040-70. 1 ttl gate + 30pf (including scope and jig) for 26lv040-55. reference levels for measuring timing: 1.5v. ac characteristics ta = 0 o c to 70 o c, vcc = 3.0v~3.6v table 9. read operations
17 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 switching test circuits switching test waveforms test points 3.0v 1.5v 1.5v 0v ac testing: inputs are driven at 3.0v for a logic "1" and 0v for a logic "0". input pulse rise and fall times are < 5ns. output input device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=100pf including jig capacitance for mx26lv040-70 (30pf for mx26lv040-55)
18 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 1. read timing waveforms addresses ce# oe# tacc we# vih vil vih vil vih vil vih vil voh vol high z high z data valid toe toeh tdf tce tacc trc outputs toh add valid
19 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 ac characteristics ta = 0 o c to 70 o c, vcc = 3.0v~3.6v table 10. erase/program operations 26lv040-55 26lv040-70 symbol parameter min. max. min. max. unit twc write cycle time (note 1) 55 70 ns tas address setup time 0 0 ns tah address hold time 45 45 ns tds data setup time 35 35 ns tdh data hold time 0 0 ns toes output enable setup time 0 0 ns tghwl read recovery time before write 0 0 ns (oe# high to we# low) tcs ce# setup time 0 0 ns tch ce# hold time 0 0 ns twp write pulse width 35 35 ns twph write pulse width high 30 30 ns twhwh1 programming operation (note 2) 55 (typ.) 55 (typ.) us twhwh2 sector erase operation (note 2) 2.4 (typ.) 2.4 (typ.) sec tvcs vcc setup time (note 1) 50 50 us tbal sector address load time 50 50 us notes: 1. not 100% tested. 2. see the "erase and programming performance" section for more information.
20 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 26l v040-55 26l v040-70 symbol parameter min. max. min. max. unit twc write cycle time (note 1) 55 70 ns tas address setup time 0 0 ns tah address hold time 45 45 ns tds data setup time 35 45 ns tdh data hold time 0 0 ns toes output enable setup time 0 0 ns tghel read recovery time before write 0 0 ns tws we# setup time 0 0 ns twh we# hold time 0 0 ns tcp ce# pulse width 35 35 ns tcph ce# pulse width high 30 30 ns twhwh1 progr amming operation(note2) 55(typ.) 55(typ.) us twhwh2 sector erase operation (note2) 2.4(typ.) 2.4(typ.) sec note: 1. not 100% tested. 2. see the "erase and programming performance" section for more information. ac characteristics ta = 0 o c to 70 o c, vcc = 3.0v~3.6v table 11. alternate ce# controlled erase/program operations
21 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 2. command write timing waveform addresses ce# oe# we# din tds tah data tdh tcs tch tcwc twph twp toes tas vcc 3v vih vil vih vil vih vil vih vil vih vil add valid
22 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 automatic programming timing waveform figure 3. automatic programming timing waveform one byte data is programmed. verify in fast algorithm and additional verification by external control are not re- quired because these operations are executed automati- cally by internal control circuit. programming comple- tion can be verified by data# polling and toggle bit check- ing after automatic programming starts. device outputs data# during programming and data# after programming on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) twc address oe# ce# a0h 555h pa pd status dout pa pa notes: 1.pa=program address, pd=program data, dout is the true data the program address tas tah tghwl tch twp tds tdh twhwh1 read status data (last two cycle) program command sequence(last two cycle) tcs twph tvcs we# data vcc
23 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 4. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes verify byte ok ? yes auto program completed data# polling from system increment address last address ? no no
24 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 5. ce# controlled program timing waveform twc twh tghel twhwh1 or 2 tcp address we# oe# ce# data q7 pa data# polling dout notes: 1. pa=program address, pd=program data, dout=data out, q7=complement of data written to device. 2. figure indicates the last two bus cycles of the command sequence. tah tas pa for program sa for sector erase 555 for chip erase tdh tds tws a0 for program 55 for erase tcph pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase
25 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 all data in chip are erased. external erase verification is not required because data is verified automatically by internal control circuit. erasure completion can be veri- fied by data# polling and toggle bit checking after auto- matic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) figure 6. automatic chip erase timing waveform automatic chip erase timing waveform twc address oe# ce# 55h 2aah 555h 10h in progress complete va va notes: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). tas tah tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tcs twph tvcs we# data vcc
26 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 7. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data pall from system auto chip erase completed
27 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 8. automatic sector erase timing waveform sector indicated by a12 to a18 are erased. external erase verify is not required because data are verified automatically by internal control circuit. erasure comple- tion can be verified by data# polling and toggle bit check- ing after automatic erase starts. device outputs 0 dur- ing erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data# polling, timing waveform) automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h notes: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). sector address n tas tah tbal tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tcs twph tvcs we# data vcc 30h
28 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 9. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data poll from system auto sector erase completed no last sector to erase yes yes no data=ffh
29 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 10. data# polling algorithm read q7~q0 add.=va(1) read q7~q0 add.=va start q7 = data ? q5 = 1 ? q7 = data ? fail pass no no (2) no ye s ye s ye s note : 1.va=valid address for programming 2.q7 should be re-checked even q5="1" because q7 may change simultaneously with q5. write operation status
30 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 11. toggle bit algorithm read q7-q0 read q7-q0 q5= 1? read q7~q0 twice program/erase operation not complete,write reset command program/erase operation complete toggle bit q6= toggle? toggle bit q6 = toggle ? no (note 1) (note 1,2) yes no no yes yes note:1.read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 change to "1". start
31 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 12. data# polling timings (during automatic algorithms) notes: 1. va=valid address. figure shows are first status cycle after command sequence, last status read cycle, and array data read cy cle. 2. ce# must be toggled when data# polling. tdf tce tacc trc tch toe toeh toh address ce# oe# we# q7 q0-q6 status data status data complement complement valid data tr u e va va va high z high z valid data tr u e
32 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 13. toggle bit timings (during automatic algorithms) notes: 1. va=valid address; not required for q6. figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. ce# must be toggled when toggle bit toggling. tdf tce tacc trc tch toe toeh high z toh address ce# oe# we# q6/q2 valid status (first raed) valid status (second read) (stops toggling) valid data va va va va valid data
33 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 figure 14. id code read timing waveform tacc tce tacc toe toh toh tdf data out c2h b5h/b6h vid vih vil add a9 add a2-a8 a10-a18 ce# oe# we# add a0 data out data q0-q7 vcc a1 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
34 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 limits parameter min. typ.(2) max.(3) units sector erase time 2.4 15 sec chip erase time 20 80 sec byte programming time 55 220 us chip programming time 18 36 sec erase/program cycles 2k (6) cycles erase and programming performance(1) latch-up characteristics note: 1. not 100% tested. 2. typical program and erase times assume the following conditions : 25 c, 3.3v vcc. programming spec. assume that all bits are programmed to checkerboard pattern. 3. maximum values are measured at vcc=3.0v, worst case temperature. maximum values are up to including 2k program/erase cycles. 4. system-level overhead is the time required to execute the command sequences for the all program command. 5. excludes 00h programming prior to erasure. (in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure) 6. min. erase/program cycles is under : 3.3v vcc, 25 c, checkerboard pattern conditions, and without baking process. min. max. input voltage with respect to gnd on acc, oe#, a9 -1.0v 12v input voltage with respect to gnd on all power pins, address pins, ce# and we# -1.0v vcc + 1.0v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time.
35 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 ordering information plastic package part no. access operating current standby current package remark time(ns) max.(ma) max.(ua) mx26lv040qc-55 55 30 100 32 pin plcc mx26lv040qc-70 70 30 100 32 pin plcc mx26lv040tc-55 55 30 100 32 pin tsop mx26lv040tc-70 70 30 100 32 pin tsop MX26LV040PC-55 55 30 100 32 pin pdip mx26lv040pc-70 70 30 100 32 pin pdip mx26lv040qc-55g 55 30 100 32 pin plcc pb-free mx26lv040qc-70g 70 30 100 32 pin plcc pb-free mx26lv040tc-55g 55 30 100 32 pin tsop pb-free mx26lv040tc-70g 70 30 100 32 pin tsop pb-free MX26LV040PC-55g 55 30 100 32 pin pdip pb-free mx26lv040pc-70g 70 30 100 32 pin pdip pb-free
36 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 package information
37 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004
38 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004
39 p/n:pm1118 mx26lv040 rev. 1.0, nov. 08, 2004 revision history revision no. description page date 1.0 1. removed "preliminary" p1 nov/08/2004 2. to added 32-pin pdip package information all
mx26lv040 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

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